1. Field of the Invention
The present invention relates to implementing programmable chips. More specifically, the present invention relates to methods and apparatus for enabling the efficient and optimized implementation of programmable chips using hardware description language source files passed through multiple tools.
2. Description of the Prior Art
Logic designers traditionally process designs represented as hardware description language source files using a variety of different tools. In one example, designs are simulated using one tool and synthesized using another tool. In many instances, the various tools are provided by different vendors. Many of the tools support and recognize the general syntax and constructs in hardware description language code.
However, some tool-specific portions of code are sometimes used during logic design. A synthesis tool provider may support tool-specific syntax and constructs that extend the features and functionality of the hardware description language for that particular tool. However, the tool-specific syntax and constructs may not be supported by other tools. For example, a synthesis tool-specific portion of code may not be recognizable by a simulation tool. Conversely, a simulation tool-specific portion of code may not be recognizable by a synthesis tool. Few mechanisms are available for allowing tool-specific code to be handled by multiple tools often from different vendors. Consequently, it is therefore desirable to provide improved methods and apparatus for handling tool-specific code.